Simulation of Asymmetric Doped High Performance Soi- Mosfets for Vlsi Cmos Technologies

Asymmetric halo and extension implantations are examined by simulation for their usability in 45 nm and 32 nm-technology high performance SOI-MOSFETs. Tilted implantations from the source side show higher saturation currents and lower drain overlap capacitances, which improve the intrinsic MOSFET power delay product. Furthermore the asymmetry leads to an inverter chain speed benefit. The stronger short channel effect, present in these devices, can be reduced by a low dose drain side halo implantation simultaneously maintaining a transistor performance improvement from asymmetric doping. This optimized transistor design is successfully transferred from the 45 nm into the 32 nm-technology. INTRODUCTION MOSFETs with asymmetric channel design are under evaluation since the nineties. The transistor used in (1) has lightly doped drain and source side halo implantations. A lower substrate current, higher punchthrough voltage and less hot carriers are the results of this asymmetry. Further research in the next decade shows similar device behavior, but the focus there is on asymmetric halo or asymmetric extension implantations (2), (3). Symmetric MOSFETs, which are used for comparison in these investigations, have mainly uniform channel profile. The halo implantation inherently improves scalability of the asymmetric transistors. But performance enhancement can also be seen comparing with symmetric halo MOSFETs (4), (5). Some of the latest high performance transistors use asymmetric channels, however only with asymmetric halo or asymmetric extension implantations (6), (7). In this study either tilted single halo or tilted extension implantations and a combination of both are investigated. Symmetric MOSFETs with dual halo-implantations are used for comparison. For the 45 nm technology, the static performance behavior is optimized by using different implantation settings. Furthermore the dynamic performance of asymmetric devices is compared to symmetric MOSFETs using the power delay product of single transistors and propagation delay time of inverter chains. Additionally the simulation results were highlighted with experimental data. The second part describes the impact of transistor scaling on the static and dynamic properties of asymmetric CMOS devices. For these purposes the 32 nm-technology with high-k gate dielectric and metal gate is used. The simulations were performed using Sentaurus TCAD from Synopsys. The quantum hydrodynamic transport model is used with a set of calibrated parameters.